1. Technical Field
The present invention relates generally to methods of fabricating semiconductor wafers. More particularly, the present invention relates to a method of forming a very shallow source-drain (S/D) extension while simultaneously doping a very narrow polysilicon gate. The present invention also includes the resulting semiconductor.
2. Related Art
Heretofore, demand for higher performance chips have driven Metal Oxide Semiconductor Field Effect Transistors (MOSFET) to shorter channel length for higher current. This high performance requires a shallow source-drain (S/D) extension and highly doped polysilicon gates completely through to the gate dielectric interface. However, as polysilicon width becomes narrower, with the aspect ratio close to 1, optimum doping of the polysilicon gate by conventional ion implantation after gate definition etching becomes very difficult.
As a result, there exists a need to have processes of fabrication in which highly doped polysilicon gates can be created with very shallow S/D extensions.
The present invention is a method of providing a layer (e.g., a substrate) including at least one polysilicon gate and at least one source/drain region; and simultaneously doping at least one gate stack and the source-drain regions. As a result, very shallow S/D extensions (i.e., less than 0.1xcexc) can be created without extra lateral scattering of dopant while at the same time providing a narrow (i.e., less than 0.2xcexc), highly doped polysilicon gate (i.e., greater than 1019 atoms of dopant/cm3) completely through to the gate dielectric interface.
The present invention also includes the resulting semiconductor exhibiting the very shallow S/D extensions and the highly doped polysilicon gate through to the gate dielectric interface.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention.